/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * include/linux/mfd/serdes/gpio.h -- GPIO for different serdes chip
 *
 * Copyright (c) 2023-2028 Rockchip Electronics Co. Ltd.
 *
 * Author: luowei <lw@rock-chips.com>
 *
 */

#ifndef __MFD_SERDES_ROHM_BU18RL82_H__
#define __MFD_SERDES_ROHM_BU18RL82_H__
#define BU18RL82_REG_RESET 0X000E

#define BU18RL82_BLOCK_EN_CLLRX0 0x0011	//h [0] 1’b1
#define BU18RL82_BLOCK_EN_LVDSTX0 0x0011	//h [1] 1’b0
#define BU18RL82_BLOCK_EN_VPLL0 0x0011	//h [3] 1’b0
#define BU18RL82_BLOCK_EN_SSCG0 0x0011	//h [4] 1’b0
#define BU18RL82_BLOCK_EN_CLLRX1 0x0012	//h [0] 1’b1
#define BU18RL82_BLOCK_EN_LVDSTX1 0x0012	//h [1] 1’b0
#define BU18RL82_BLOCK_EN_VPLL1 0x0012	//h [3] 1’b0
#define BU18RL82_BLOCK_EN_SSCG1 0x0012	//h [4] 1’b0
#define BU18RL82_BLOCK_EN_CLLTX 0x0013	//h [0] 1’b0
#define BU18RL82_BLOCK_EN_FSAFETY 0x0013	//h [1] 1’b0

#define BU18RL82_IO_SW_GPIO0 0x0057		//h [2:1] 2’b00
#define BU18RL82_IO_OEN_GPIO0 0x0057	//h [3] 1’b1
#define BU18RL82_IO_PDEN_GPIO0 0x0057	//h [4] 1’b1
#define BU18RL82_IO_SW_GPIO1 0x005A		//h [2:1] 2’b00
#define BU18RL82_IO_OEN_GPIO1 0x005A	//h [3] 1’b1
#define BU18RL82_IO_PDEN_GPIO1 0x005A	//h [4] 1’b1
#define BU18RL82_IO_SW_GPIO2 0x005D		//h [2:1] 2’b00
#define BU18RL82_IO_OEN_GPIO2 0x005D	//h [3] 1’b1
#define BU18RL82_IO_PDEN_GPIO2 0x005D	//h [4] 1’b1
#define BU18RL82_IO_SW_GPIO3 0x0060		//h [2:1] 2’b00
#define BU18RL82_IO_OEN_GPIO3 0x0060	//h [3] 1’b1
#define BU18RL82_IO_PDEN_GPIO3 0x0060	//h [4] 1’b1
#define BU18RL82_IO_SW_GPIO4 0x0063		//h [2:1] 2’b00
#define BU18RL82_IO_OEN_GPIO4 0x0063	//h [3] 1’b1
#define BU18RL82_IO_PDEN_GPIO4 0x0063	//h [4] 1’b1
#define BU18RL82_IO_SW_GPIO5 0x0066		//h [2:1] 2’b00
#define BU18RL82_IO_OEN_GPIO5 0x0066	//h [2:1] 2’b00
#define BU18RL82_IO_PDEN_GPIO5 0x0066	//h [3] 1’b1
#define BU18RL82_IO_SW_GPIO6 0x0069		//h [2:1] 2’b00
#define BU18RL82_IO_OEN_GPIO6 0x0069	//h [3] 1’b1
#define BU18RL82_IO_PDEN_GPIO6 0x0069	//h [4] 1’b1
#define BU18RL82_IO_SW_GPIO7 0x006C		//h [2:1] 2’b00
#define BU18RL82_IO_OEN_GPIO7 0x006C	//h [3] 1’b1
#define BU18RL82_IO_PDEN_GPIO7 0x006C	//h [4] 1’b1

/*
 * gpio register for define connection with des gpiox,
 * 11bits such as 0x002c:002b=[b2..b0 b7...b0]
 * default value:
 * ser gpio0-->des gpio0
 * ser gpio1-->des gpio1
 * ser gpio2-->des gpio2
 * ser gpio3-->des gpio3
 */
#define BU18RL82_GPIO_SEL0_HIGH 0x0059	//h [2:0],
#define BU18RL82_GPIO_SEL0_LOW 0x0058	//h [7:0]} 11’h002
#define BU18RL82_GPIO_SEL1_HIGH 0x005C	//h [2:0],
#define BU18RL82_GPIO_SEL1_LOW 0x005B	//h [7:0]} 11’h003
#define BU18RL82_GPIO_SEL2_HIGH 0x005F	//h [2:0],
#define BU18RL82_GPIO_SEL2_LOW 0x005E	//h [7:0]} 11’h012
#define BU18RL82_GPIO_SEL3_HIGH 0x0062	//h [2:0],
#define BU18RL82_GPIO_SEL3_LOW 0x0061	//h [7:0]} 11’h013
#define BU18RL82_GPIO_SEL4_HIGH 0x0065	//h [2:0],
#define BU18RL82_GPIO_SEL4_LOW 0x0064	//h [7:0]} 11’h006
#define BU18RL82_GPIO_SEL5_HIGH 0x0068	//h [2:0],
#define BU18RL82_GPIO_SEL5_LOW 0x0067	//h [7:0]} 11’h007
#define BU18RL82_GPIO_SEL6_HIGH 0x006B	//h [2:0],
#define BU18RL82_GPIO_SEL6_LOW 0x006A	//h [7:0]} 11’h008
#define BU18RL82_GPIO_SEL7_HIGH 0x006E	//h [2:0],
#define BU18RL82_GPIO_SEL7_LOW 0x006D	//h [7:0]} 11’h009

/*gpio register for define bu18rl82 gpio pin, and gpio0 to gpio0 default*/
#define BU18RL82_BCCTX0__SEL_GPI0 0x042B	//h [5:0] 6’h02
#define BU18RL82_BCCTX0__SEL_GPI1 0x042C	//h [5:0] 6’h03
#define BU18RL82_BCCTX0__SEL_GPI2 0x042D	//h [5:0] 6’h04
#define BU18RL82_BCCTX0__SEL_GPI3 0x042E	//h [5:0] 6’h05
#define BU18RL82_BCCTX0__SEL_GPI4 0x042F	//h [5:0] 6’h06
#define BU18RL82_BCCTX0__SEL_GPI5 0x0430	//h [5:0] 6’h07
#define BU18RL82_BCCTX0__SEL_GPI6 0x0431	//h [5:0] 6’h08
#define BU18RL82_BCCTX0__SEL_GPI7 0x0432	//h [5:0] 6’h09
#define BU18RL82_BCCTX1__SEL_GPI0 0x052B	//h [5:0] 6’h02
#define BU18RL82_BCCTX1__SEL_GPI1 0x052C	//h [5:0] 6’h03
#define BU18RL82_BCCTX1__SEL_GPI2 0x052D	//h [5:0] 6’h04
#define BU18RL82_BCCTX1__SEL_GPI3 0x052E	//h [5:0] 6’h05
#define BU18RL82_BCCTX1__SEL_GPI4 0x052F	//h [5:0] 6’h06
#define BU18RL82_BCCTX1__SEL_GPI5 0x0530	//h [5:0] 6’h07
#define BU18RL82_BCCTX1__SEL_GPI6 0x0531	//h [5:0] 6’h08
#define BU18RL82_BCCTX1__SEL_GPI7 0x0532	//h [5:0] 6’h09

#define BU18RL82_IEN_CLLRX0_LINK_UNLOCK 0x0109	//h [1] 1’b0
#define BU18RL82_IEN_CLLRX0_BIT_ERR 0x0109		//h [3] 1’b0
#define BU18RL82_IEN_CLLRX0_ERR_CNT_OVF 0x0109	//h [4] 1’b0
#define BU18RL82_IEN_CLLRX1_LINK_UNLOCK 0x010B	//h [1] 1’b0
#define BU18RL82_IEN_CLLRX1_BIT_ERR 0x010B		//h [3] 1’b0
#define BU18RL82_IEN_CLLRX1_ERR_CNT_OVF 0x010B	//h [4] 1’b0
#define BU18RL82_IEN_FCCRX0_CRCERR 0x010D		//h [0] 1’b0
#define BU18RL82_IEN_FCCRX1_CRCERR 0x010E		//h [0] 1’b0
#define BU18RL82_IEN_BCCDES0_ERR_CRC 0x010F		//h [3] 1’b0
#define BU18RL82_IEN_CLLRX0_CRCERR_R  0x0110	//h [0] 1’b0
#define BU18RL82_IEN_CLLRX0_CRCERR_G 0x0110		//h [1] 1’b0
#define BU18RL82_IEN_CLLRX0_CRCERR_B 0x0110		//h [2] 1’b0
#define BU18RL82_IEN_CLLRX1_CRCERR_R 0x0111		//h [0] 1’b0
#define BU18RL82_IEN_CLLRX1_CRCERR_G 0x0111		//h [1] 1’b0
#define BU18RL82_IEN_CLLRX1_CRCERR_B 0x0111		//h [2] 1’b0
#define BU18RL82_IEN_FS_IMG_STATUS0 0x0112		//h [0] 1’b0
#define BU18RL82_IEN_FS_IMG_STATUS1 0x0112		//h [1] 1’b0
#define BU18RL82_IEN_FS_IMG_STATUS2 0x0112		//h [2] 1’b0
#define BU18RL82_IEN_FS_IMG_STATUS3 0x0112		//h [3] 1’b0
#define BU18RL82_IEN_FS_IMG_ERR_REGION0 0x0113	//h [0] 1’b0
#define BU18RL82_IEN_FS_IMG_ERR_REGION1 0x0113	//h [1] 1’b0
#define BU18RL82_IEN_FS_IMG_ERR_REGION2 0x0113	//h [2] 1’b0
#define BU18RL82_IEN_FS_IMG_ERR_REGION3 0x0113	//h [3] 1’b0
#define BU18RL82_IEN_FS_IMG_ERR_REGION4 0x0113	//h [4] 1’b0
#define BU18RL82_IEN_FS_IMG_ERR_REGION5 0x0113	//h [5] 1’b0
#define BU18RL82_IEN_FS_IMG_ERR_REGION6 0x0113	//h [6] 1’b0
#define BU18RL82_IEN_FS_IMG_ERR_REGION7 0x0113	//h [7] 1’b0
#define BU18RL82_IEN_IO_STUCK_GPIO0 0x0114		//h [0] 1’b0
#define BU18RL82_IEN_IO_STUCK_GPIO1 0x0114		//h [1] 1’b0
#define BU18RL82_IEN_IO_STUCK_GPIO2 0x0114		//h [2] 1’b0
#define BU18RL82_IEN_IO_STUCK_GPIO3 0x0114		//h [3] 1’b0
#define BU18RL82_IEN_IO_STUCK_GPIO4 0x0114		//h [4] 1’b0
#define BU18RL82_IEN_IO_STUCK_GPIO5 0x0114		//h [5] 1’b0
#define BU18RL82_IEN_IO_STUCK_GPIO6 0x0114		//h [6] 1’b0
#define BU18RL82_IEN_IO_STUCK_GPIO7 0x0114		//h [7] 1’b0
#define BU18RL82_IEN_IO_STUCK_IRQ 0x0115		//h [1] 1’b0
#define BU18RL82_IEN_IDS_UNSTABLE 0x0115		//h [7] 1’b0
#define BU18RL82_IEN_I2C_A_TIMEOUT 0x0116		//h [0] 1’b0
#define BU18RL82_IEN_I2C_A_XMIT_ERR 0x0116		//h [1] 1’b0
#define BU18RL82_IEN_REGCRC_ERR_PAGE0 0x0117	//h [0] 1’b0
#define BU18RL82_IEN_REGCRC_ERR_PAGE1 0x0117	//h [1] 1’b0
#define BU18RL82_IEN_REGCRC_ERR_PAGE2 0x0117	//h [2] 1’b0
#define BU18RL82_IEN_REGCRC_ERR_PAGE3 0x0117	//h [3] 1’b0
#define BU18RL82_IEN_REGCRC_ERR_PAGE4 0x0117	//h [4] 1’b0
#define BU18RL82_IEN_REGCRC_ERR_PAGE5 0x0117	//h [5] 1’b0
#define BU18RL82_IEN_REGCRC_ERR_PAGE6 0x0117	//h [6] 1’b0
#define BU18RL82_IEN_REGCRC_ERR_PAGE7 0x0117	//h [7] 1’b0
#define BU18RL82_IEN_CLKDETECT_CLKIN_STOP 0x0118			//h [0] 1’b0
#define BU18RL82_IEN_CLKDETECT_CLKIN_UNLOCK 0x0118			//h [1] 1’b0
#define BU18RL82_IEN_CLKDETECT_OSC_STOP 0x0118				//h [4] 1’b0
#define BU18RL82_IEN_CLKDETECT_OSC_UNLOCK 0x0118			//h [5] 1’b0
#define BU18RL82_IEN_CLKDETECT_CLLRX0_PCLK_STOP 0x0119		//h [0] 1’b0
#define BU18RL82_IEN_CLKDETECT_CLLRX0_PCLK_UNLOCK 0x0119	//h [1] 1’b0
#define BU18RL82_IEN_CLKDETECT_LVDSTX0_CLK_STOP 0x0119		//h [4] 1’b0
#define BU18RL82_IEN_CLKDETECT_LVDSTX0_CLK_UNLOCK 0x0119	//h [5] 1’b0
#define BU18RL82_IEN_CLKDETECT_CLLRX1_PCLK_STOP 0x011A		//h [0] 1’b0
#define BU18RL82_IEN_CLKDETECT_CLLRX1_PCLK_UNLOCK 0x011A	//h [1] 1’b0
#define BU18RL82_IEN_CLKDETECT_LVDSTX1_CLK_STOP 0x011A		//h [4] 1’b0
#define BU18RL82_IEN_CLKDETECT_LVDSTX1_CLK_UNLOCK 0x011A	//h [5] 1’b0
#define BU18RL82_IEN_CLKDETECT_CLLTX0_SCLK_STOP 0x011B		//h [0] 1’b0
#define BU18RL82_IEN_CLKDETECT_CLLTX0_SCLK_UNLOCK 0x011B	//h [1] 1’b0
#define BU18RL82_IEN_CLKDETECT_CLLTX0_PLLREF_STOP 0x011B	//h [4] 1’b0
#define BU18RL82_IEN_CLKDETECT_CLLTX0_PLLREF_UNLOCK 0x011B	//h [5] 1’b0
#define BU18RL82_IEN_CLKDETECT_LVDSTX0_PLLREF_STOP 0x011C	//h [0] 1’b0
#define BU18RL82_IEN_CLKDETECT_LVDSTX0_PLLREF_UNLOCK0x011C	//h [1] 1’b0
#define BU18RL82_IEN_CLKDETECT_LVDSTX1_PLLREF_STOP 0x011C	//h [4] 1’b0
#define BU18RL82_IEN_CLKDETECT_LVDSTX1_PLLREF_UNLOCK 0x011C	//h [5] 1’b0

#define BU18RL82_ISR_CLEAR_ALL 0x0105			//h [0] 1’b0
#define BU18RL82_ISR_CLLRX0_LINK_UNLOCK 0x0129	//h [1] 1’b0
#define BU18RL82_ISR_CLLRX0_BIT_ERR 0x0129		//h [3] 1’b0
#define BU18RL82_ISR_CLLRX0_ERR_CNT_OVF 0x0129	//h [4] 1’b0
#define BU18RL82_ISR_CLLRX1_ERR_CNT_OVF 0x012B	//h [4] 1’b0
#define BU18RL82_ISR_CLLRX1_LINK_UNLOCK 0x012B	//h [1] 1’b0
#define BU18RL82_ISR_CLLRX1_BIT_ERR 0x012B		//h [3] 1’b0
#define BU18RL82_ISR_FCCRX0_CRCERR 0x012D		//h [0] 1’b0
#define BU18RL82_ISR_FCCRX1_CRCERR 0x012E		//h [0] 1’b0
#define BU18RL82_ISR_BCCDES0_ERR_CRC 0x012F		//h [3] 1’b0
#define BU18RL82_ISR_CLLRX0_CRCERR_R  0x0130	//h [0] 1’b0
#define BU18RL82_ISR_CLLRX0_CRCERR_G 0x0130		//h [1] 1’b0
#define BU18RL82_ISR_CLLRX0_CRCERR_B 0x0130		//h [2] 1’b0
#define BU18RL82_ISR_CLLRX1_CRCERR_R 0x0131		//h [0] 1’b0
#define BU18RL82_ISR_CLLRX1_CRCERR_G 0x0131		//h [1] 1’b0
#define BU18RL82_ISR_CLLRX1_CRCERR_B 0x0131		//h [2] 1’b0
#define BU18RL82_ISR_FS_IMG_STATUS0 0x0132		//h [0] 1’b0
#define BU18RL82_ISR_FS_IMG_STATUS1 0x0132		//h [1] 1’b0
#define BU18RL82_ISR_FS_IMG_STATUS2 0x0132		//h [2] 1’b0
#define BU18RL82_ISR_FS_IMG_STATUS3 0x0132		//h [3] 1’b0
#define BU18RL82_ISR_FS_IMG_ERR_REGION0 0x0133	//h [0] 1’b0
#define BU18RL82_ISR_FS_IMG_ERR_REGION1 0x0133	//h [1] 1’b0
#define BU18RL82_ISR_FS_IMG_ERR_REGION2 0x0133	//h [2] 1’b0
#define BU18RL82_ISR_FS_IMG_ERR_REGION3 0x0133	//h [3] 1’b0
#define BU18RL82_ISR_FS_IMG_ERR_REGION4 0x0133	//h [4] 1’b0
#define BU18RL82_ISR_FS_IMG_ERR_REGION5 0x0133	//h [5] 1’b0
#define BU18RL82_ISR_FS_IMG_ERR_REGION6 0x0133	//h [6] 1’b0
#define BU18RL82_ISR_FS_IMG_ERR_REGION7 0x0133	//h [7] 1’b0
#define BU18RL82_ISR_IO_STUCK_GPIO0 0x0134	//h [0] 1’b0
#define BU18RL82_ISR_IO_STUCK_GPIO1 0x0134	//h [1] 1’b0
#define BU18RL82_ISR_IO_STUCK_GPIO2 0x0134	//h [2] 1’b0
#define BU18RL82_ISR_IO_STUCK_GPIO3 0x0134	//h [3] 1’b0
#define BU18RL82_ISR_IO_STUCK_GPIO4 0x0134	//h [4] 1’b0
#define BU18RL82_ISR_IO_STUCK_GPIO5 0x0134	//h [5] 1’b0
#define BU18RL82_ISR_IO_STUCK_GPIO6 0x0134	//h [6] 1’b0
#define BU18RL82_ISR_IO_STUCK_GPIO7 0x0134	//h [7] 1’b0
#define BU18RL82_ISR_IO_STUCK_IRQ 0x0135	//h [1] 1’b0
#define BU18RL82_ISR_IDS_UNSTABLE 0x0135	//h [7] 1’b0
#define BU18RL82_ISR_I2C_A_TIMEOUT 0x0136	//h [0] 1’b0
#define BU18RL82_ISR_I2C_A_XMIT_ERR 0x0136	//h [1] 1’b0
#define BU18RL82_ISR_REGCRC_ERR_PAGE0 0x0137	//h [0] 1’b0
#define BU18RL82_ISR_REGCRC_ERR_PAGE1 0x0137	//h [1] 1’b0
#define BU18RL82_ISR_REGCRC_ERR_PAGE2 0x0137	//h [2] 1’b0
#define BU18RL82_ISR_REGCRC_ERR_PAGE3 0x0137	//h [3] 1’b0
#define BU18RL82_ISR_REGCRC_ERR_PAGE4 0x0137	//h [4] 1’b0
#define BU18RL82_ISR_REGCRC_ERR_PAGE5 0x0137	//h [5] 1’b0
#define BU18RL82_ISR_REGCRC_ERR_PAGE6 0x0137	//h [6] 1’b0
#define BU18RL82_ISR_REGCRC_ERR_PAGE7 0x0137	//h [7] 1’b0
#define BU18RL82_ISR_CLKDETECT_CLKIN_STOP 0x0138			//h [0] 1’b0
#define BU18RL82_ISR_CLKDETECT_CLKIN_UNLOCK 0x0138			//h [1] 1’b0
#define BU18RL82_ISR_CLKDETECT_OSC_STOP 0x0138				//h [4] 1’b0
#define BU18RL82_ISR_CLKDETECT_OSC_UNLOCK 0x0138			//h [5] 1’b0
#define BU18RL82_ISR_CLKDETECT_CLLRX0_PCLK_STOP 0x0139		//h [0] 1’b0
#define BU18RL82_ISR_CLKDETECT_CLLRX0_PCLK_UNLOCK 0x0139	//h [1] 1’b0
#define BU18RL82_ISR_CLKDETECT_LVDSTX0_CLK_STOP 0x0139		//h [4] 1’b0
#define BU18RL82_ISR_CLKDETECT_LVDSTX0_CLK_UNLOCK 0x0139	//h [5] 1’b0
#define BU18RL82_ISR_CLKDETECT_CLLRX1_PCLK_STOP 0x013A		//h [0] 1’b0
#define BU18RL82_ISR_CLKDETECT_CLLRX1_PCLK_UNLOCK 0x013A	//h [1] 1’b0
#define BU18RL82_ISR_CLKDETECT_LVDSTX1_CLK_STOP 0x013A		//h [4] 1’b0
#define BU18RL82_ISR_CLKDETECT_LVDSTX1_CLK_UNLOCK 0x013A	//h [5] 1’b0
#define BU18RL82_ISR_CLKDETECT_CLLTX0_SCLK_STOP 0x013B		//h [0] 1’b0
#define BU18RL82_ISR_CLKDETECT_CLLTX0_SCLK_UNLOCK 0x013B	//h [1] 1’b0
#define BU18RL82_ISR_CLKDETECT_CLLTX0_PLLREF_STOP 0x013B	//h [4] 1’b0
#define BU18RL82_ISR_CLKDETECT_CLLTX0_PLLREF_UNLOCK 0x013B	//h [5] 1’b0
#define BU18RL82_ISR_CLKDETECT_LVDSTX0_PLLREF_STOP 0x013C	//h [0] 1’b0
#define BU18RL82_ISR_CLKDETECT_LVDSTX0_PLLREF_UNLOCK0x013C	//h [1] 1’b0
#define BU18RL82_ISR_CLKDETECT_LVDSTX1_PLLREF_STOP 0x013C	//h [4] 1’b0
#define BU18RL82_ISR_CLKDETECT_LVDSTX1_PLLREF_UNLOCK 0x013C	//h [5] 1’b0

struct bu18rl82_gpio_sw_reg {
	unsigned int reg;
	unsigned int mask;	//2/4/6/8ma
};

struct bu18rl82_gpio_oen_reg {
	unsigned int reg;
	unsigned int mask;	//0:output 1:input
};

struct bu18rl82_gpio_pden_reg {
	unsigned int reg;
	unsigned int mask;	//0:no pulldown 1:connect pulldown
};

struct bu18rl82_gpio_id_low_reg {
	unsigned int reg;
	unsigned int mask;	//b2b1b0
};

struct bu18rl82_gpio_id_high_reg {
	unsigned int reg;
	unsigned int mask;	//b11b10b9b8b7b6b5b4b3
};

static const struct bu18rl82_gpio_sw_reg bu18rl82_gpio_sw[8] = {
	{BU18RL82_IO_SW_GPIO0, BIT(2) | BIT(1)},
	{BU18RL82_IO_SW_GPIO1, BIT(2) | BIT(1)},
	{BU18RL82_IO_SW_GPIO2, BIT(2) | BIT(1)},
	{BU18RL82_IO_SW_GPIO3, BIT(2) | BIT(1)},
	{BU18RL82_IO_SW_GPIO4, BIT(2) | BIT(1)},
	{BU18RL82_IO_SW_GPIO5, BIT(2) | BIT(1)},
	{BU18RL82_IO_SW_GPIO6, BIT(2) | BIT(1)},
	{BU18RL82_IO_SW_GPIO7, BIT(2) | BIT(1)},
};

static const struct bu18rl82_gpio_oen_reg bu18rl82_gpio_oen[8] = {
	{BU18RL82_IO_OEN_GPIO0, BIT(3)},
	{BU18RL82_IO_OEN_GPIO1, BIT(3)},
	{BU18RL82_IO_OEN_GPIO2, BIT(3)},
	{BU18RL82_IO_OEN_GPIO3, BIT(3)},
	{BU18RL82_IO_OEN_GPIO4, BIT(3)},
	{BU18RL82_IO_OEN_GPIO5, BIT(3)},
	{BU18RL82_IO_OEN_GPIO6, BIT(3)},
	{BU18RL82_IO_OEN_GPIO7, BIT(3)},
};

static const struct bu18rl82_gpio_pden_reg bu18rl82_gpio_pden[8] = {
	{BU18RL82_IO_PDEN_GPIO0, BIT(4)},
	{BU18RL82_IO_PDEN_GPIO1, BIT(4)},
	{BU18RL82_IO_PDEN_GPIO2, BIT(4)},
	{BU18RL82_IO_PDEN_GPIO3, BIT(4)},
	{BU18RL82_IO_PDEN_GPIO4, BIT(4)},
	{BU18RL82_IO_PDEN_GPIO5, BIT(4)},
	{BU18RL82_IO_PDEN_GPIO6, BIT(4)},
	{BU18RL82_IO_PDEN_GPIO7, BIT(4)},
};

static const struct bu18rl82_gpio_id_low_reg bu18rl82_gpio_id_low[8] = {
	{BU18RL82_GPIO_SEL0_LOW, GENMASK(7, 0)},
	{BU18RL82_GPIO_SEL1_LOW, GENMASK(7, 0)},
	{BU18RL82_GPIO_SEL2_LOW, GENMASK(7, 0)},
	{BU18RL82_GPIO_SEL3_LOW, GENMASK(7, 0)},
	{BU18RL82_GPIO_SEL4_LOW, GENMASK(7, 0)},
	{BU18RL82_GPIO_SEL5_LOW, GENMASK(7, 0)},
	{BU18RL82_GPIO_SEL6_LOW, GENMASK(7, 0)},
	{BU18RL82_GPIO_SEL7_LOW, GENMASK(7, 0)},
};

static const struct bu18rl82_gpio_id_high_reg bu18rl82_gpio_id_high[8] = {
	{BU18RL82_GPIO_SEL0_HIGH, GENMASK(2, 0)},
	{BU18RL82_GPIO_SEL1_HIGH, GENMASK(2, 0)},
	{BU18RL82_GPIO_SEL2_HIGH, GENMASK(2, 0)},
	{BU18RL82_GPIO_SEL3_HIGH, GENMASK(2, 0)},
	{BU18RL82_GPIO_SEL4_HIGH, GENMASK(2, 0)},
	{BU18RL82_GPIO_SEL5_HIGH, GENMASK(2, 0)},
	{BU18RL82_GPIO_SEL6_HIGH, GENMASK(2, 0)},
	{BU18RL82_GPIO_SEL7_HIGH, GENMASK(2, 0)},
};

struct bu18rl82_ien_reg {
	unsigned int reg;
	unsigned int ien;
};

struct bu18rl82_isr_reg {
	unsigned int reg;
	unsigned int isr;
};

struct bu18rl82_gpio_reg {
	unsigned int reg;
	unsigned int val;
};

static const struct bu18rl82_ien_reg bu18rl82_reg_ien[18] = {
	{BU18RL82_IEN_CLLRX0_LINK_UNLOCK,
	 BIT(1) | BIT(3) | BIT(4)},
	{BU18RL82_IEN_CLLRX1_LINK_UNLOCK,
	 BIT(1) | BIT(3) | BIT(4)},
	{BU18RL82_IEN_FCCRX0_CRCERR, BIT(0)},
	{BU18RL82_IEN_FCCRX1_CRCERR, BIT(0)},

	{BU18RL82_IEN_BCCDES0_ERR_CRC, BIT(3)},
	{BU18RL82_IEN_CLLRX0_CRCERR_R,
	 BIT(0) | BIT(1) | BIT(2)},
	{BU18RL82_IEN_CLLRX1_CRCERR_R,
	 BIT(0) | BIT(1) | BIT(2)},

	{BU18RL82_IEN_FS_IMG_STATUS0,
	 BIT(0) | BIT(1) | BIT(2) | BIT(3)},
	{BU18RL82_IEN_FS_IMG_ERR_REGION0, 0xff},
	{BU18RL82_IEN_IO_STUCK_GPIO0, 0xff},
	{BU18RL82_IEN_IO_STUCK_IRQ, BIT(1) | BIT(7)},
	{BU18RL82_IEN_I2C_A_TIMEOUT, BIT(0) | BIT(1)},

	{BU18RL82_IEN_REGCRC_ERR_PAGE0, 0xff},
	{BU18RL82_IEN_CLKDETECT_CLKIN_STOP,
	 BIT(0) | BIT(1) | BIT(4) | BIT(5)},
	{BU18RL82_IEN_CLKDETECT_CLLRX0_PCLK_STOP,
	 BIT(0) | BIT(1) | BIT(4) | BIT(5)},
	{BU18RL82_IEN_CLKDETECT_CLLRX1_PCLK_STOP,
	 BIT(0) | BIT(1) | BIT(4) | BIT(5)},
	{BU18RL82_IEN_CLKDETECT_CLLTX0_SCLK_STOP,
	 BIT(0) | BIT(1) | BIT(4) | BIT(5)},
	{BU18RL82_IEN_CLKDETECT_LVDSTX0_PLLREF_STOP,
	 BIT(0) | BIT(1) | BIT(4) | BIT(5)},
};

static const struct bu18rl82_isr_reg bu18rl82_reg_isr[18] = {
	{BU18RL82_ISR_CLLRX0_LINK_UNLOCK,
	 BIT(1) | BIT(3) | BIT(4)},
	{BU18RL82_ISR_CLLRX1_LINK_UNLOCK,
	 BIT(1) | BIT(3) | BIT(4)},
	{BU18RL82_ISR_FCCRX0_CRCERR, BIT(0)},
	{BU18RL82_ISR_FCCRX1_CRCERR, BIT(0)},

	{BU18RL82_ISR_BCCDES0_ERR_CRC, BIT(3)},
	{BU18RL82_ISR_CLLRX0_CRCERR_R,
	 BIT(0) | BIT(1) | BIT(2)},
	{BU18RL82_ISR_CLLRX1_CRCERR_R,
	 BIT(0) | BIT(1) | BIT(2)},

	{BU18RL82_ISR_FS_IMG_STATUS0,
	 BIT(0) | BIT(1) | BIT(2) | BIT(3)},
	{BU18RL82_ISR_FS_IMG_ERR_REGION0, 0xff},
	{BU18RL82_ISR_IO_STUCK_GPIO0, 0xff},
	{BU18RL82_ISR_IO_STUCK_IRQ, BIT(1) | BIT(7)},
	{BU18RL82_ISR_I2C_A_TIMEOUT, BIT(0) | BIT(1)},

	{BU18RL82_ISR_REGCRC_ERR_PAGE0, 0xff},
	{BU18RL82_ISR_CLKDETECT_CLKIN_STOP,
	 BIT(0) | BIT(1) | BIT(4) | BIT(5)},
	{BU18RL82_ISR_CLKDETECT_CLLRX0_PCLK_STOP,
	 BIT(0) | BIT(1) | BIT(4) | BIT(5)},
	{BU18RL82_ISR_CLKDETECT_CLLRX1_PCLK_STOP,
	 BIT(0) | BIT(1) | BIT(4) | BIT(5)},
	{BU18RL82_ISR_CLKDETECT_CLLTX0_SCLK_STOP,
	 BIT(0) | BIT(1) | BIT(4) | BIT(5)},
	{BU18RL82_ISR_CLKDETECT_LVDSTX0_PLLREF_STOP,
	 BIT(0) | BIT(1) | BIT(4) | BIT(5)},
};

#endif
